Unit Delay
Acts as a buffer of one sampling period
Category: Dynamics
Description:
The Unit Delay block allows the user to use the signal one sample time delayed. The sample time is equal to the Simulation Step time. Figures 1 and 2 show a Unit Delay block in a diagram with a Simulation Step time of 0.2s.
Figure 1 - Unit delay example
Figure 2 - Sine wave and its delayed version
In this example, the Unit Delay uses zero as Initial Condition.
Parameters:
The Unit Delay block takes one sample time to output the signal received by the input port. Due to this behavior, it is necessary to parameterize the initial condition.
Ports:
Input
The signal flowing into this port is assigned to a buffer at the current sampling instant.
Data Types:
Output
The signal flowing from this port is defined by:
Where:
- : Output Signal.
- : Input Signal.
- : Initial Condition Value.
- : Discrete time index.
Data Types:
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