Unit Delay

Acts as a buffer of one sampling period

Category: Dynamics

Description:

The Unit Delay block allows the user to use the signal one sample time delayed. Figures 1 and 2 show a Unit Delay block in a diagram with a Task period of 0.2s.

Figure 1 - Unit delay example

Figure 2 - Ramp signal and its delayed version

In this example, the Unit Delay uses zero as Initial Condition.

Parameters:

The Unit Delay block takes one sample time to output the signal received by the input port. Due to this behavior, it is necessary to parameterize the initial condition.

Ports:

Input

The signal flowing into this port is assigned to a buffer at the current sampling instant.

Data Types:
Output

The signal flowing from this port is defined by:

y={IC,k=0xk1,k>0y=\begin{cases} I_C &&,&&k=0 \\x_{k-1}&&,&&k>0\end{cases}

Where:

  • yy
    : Output Signal.
  • xx
    : Input Signal.
  • ICI_C
    : Initial Condition.
  • kk
    : Discrete time index.

Data Types:

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